Pinpoint Vertical Integration of Spintronic Devices for Reconfigurable Resiliency

While technology scaling increases density and near threshold voltage operation slashes energy consumption, serious reliability concerns such as radiation-induced soft errors and timing violations due to Process Variation (PV) become exacerbated. For instance, the probability of single upsets, and more realistically, multiple upsets, is projected to increase several fold at sealevel for sub-10nm technology nodes. Meanwhile, the existing error mitigation techniques utilize selective spatial or temporal redundancy and/or rollback, which rely heavily on CMOS-based golden elements susceptible to soft errors, or else require area-consuming fortification to mitigate such possibilities. Meanwhile spintronic devices offer radiation immunity and incur near-zero standby energy consumption, making them ideal elements for these golden components. They also realize a fabric of amorphous resources in standby mode to regain lost functionality from hard or intermittent faults, and PV. The challenge is to provide a flexible yet effective mapping of spintronic devices to adapt their functionality for resilience at runtime. Magnetic Tunnel Junction (MTJ)-based Lookup Tables (LUTs) are proposed to be placed at critical points of an ASIC to implement various logic functions as a runtime adaptable fabric under middleware control. Radiation immunity of MTJ devices decrease the susceptibility of these golden elements of the design to radiation-induced errors. Moreover, the pinpointed magnetic LUTs provides the fabric with sufficient reconfigurability features to mitigate PV. The fabric will be leveraged for fault detection and recovery using the adaptive self-healing approaches. Synthesis tools such as Synopsys Design Compiler will be utilized to determine the composition of the fabric, as well as synthesizing and optimizing the HDL codes. MTJs comprising the storage elements in the adaptable LUTs are vertically-integrated as a backend process of typical CMOS fabrication. In addition to soft error immunity, this significantly reduces the area cost of the redundancy. PINPOINT VERTICAL INTEGRATION OF SPINTRONIC DEVICES FOR RECONFIGURABLE RESILIENCY